The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory).
A semiconductor memory device called DRAM requires rewriting of memory cells and precharging of bit lines in every cycle time. Therefore, the cycle time required by the DRAM is about twice the access time. There is technology for reducing the cycle time to approximately the same length as that of the access time by apparently hiding precharge operation of the bit lines. One example of this technology is to cause two internal ports to interleave with each other by using the memory cells each including two transistors and a single capacitor. FIG. 19 schematically shows the structure of a DRAM using this technology. Each memory cell MC1 to MC4 of the DRAM includes two transistors Ta, Tb and a single capacitor C. This DRAM causes the following two ports A, B to interleave with each other: the port A formed by the path including transistor Ta, bit line BLa1 or BLa2, data bus DBa, and read amplifier and write driver 1103a; and the port B formed by the path including transistor Tb, bit line BLb1 or BLb2, data bus DBb, and read amplifier and write driver 1103b. Hereinafter, interleave operation will be described regarding the case where data is read from a memory cell.
A row decoder 1101 activates a word line WLa1, whereby the transistors Ta of the memory cells MC1, MC3 are turned ON. As a result, data stored in the capacitors C of the memory cells MC1, MC3 are read to the bit lines BLa1, BLa2 and then amplified by a sense amplifier (not shown). A column decoder 1102a selects the bit line BLa1 and connects the bit line BLa1 to the data bus DBa. As a result, the data read from the memory cell MC1 to the bit line BLa1 is transferred to the data bus DBa. The data read to the bit lines BLa1, BLa2 are rewritten to the memory cells MC1, MC3. The row decoder 1101 then inactivates the word line WLa1, whereby the transistors Ta of the memory cells MC1, MC3 are turned OFF. The bit lines BLb1, BLb2 are precharged during the above operation.
The data transferred to the data bus DBa is amplified by the read amplifier and write driver 1103a for output to an input/output (I/O) buffer 1104. The I/O buffer 1104 outputs the amplified data to the outside. On the other hand, the row decoder 1101 activates a word line WLb2, whereby the transistors Tb of the memory cells MC2, MC4 are turned ON. As a result, data stored in the capacitors C of the memory cells MC2, MC4 are read to the bit lines BLb1, BLb2 and amplified by a sense amplifier (not shown). A column decoder 1102b selects the bit line BLb1 and connects the bit line BLb1 to the data bus DBb. As a result, the data read from the memory cell MC2 to the bit line BLb1 is transferred to the data bus DBb. The data read to the bit lines BLb1, BLb2 are rewritten to the memory cells MC2, MC4. The row decoder 1101 then inactivates the word line WLb2, whereby the transistors Tb of the memory cells MC2, MC4 are turned OFF. The bit lines BLa1, BLa2 are precharged during the above operation.
The data transferred to the data bus DBb is amplified by the read amplifier and write driver 1103b for output to the I/O buffer 1104. The I/O buffer 1104 outputs the amplified data to the outside.
Such interleave operation of the two internal ports apparently hides precharge operation of the bit lines, thereby reducing the cycle time to approximately the same length as that of the access time.
The DRAM of FIG. 19 has a read amplifier and write driver for each port. In other words, the DRAM of FIG. 19 has a read amplifier and write driver 1103a for the port A and a read amplifier and write driver 1103b for the port B. This increases the area of peripheral circuitry including the read amplifiers and write drivers if a specification using a large bit width is required (e.g., an embedded DRAM).